1. Field of the Invention
The present invention is directed to electrostatic discharge protection for electronic circuits; more particularly, the invention is directed to electrostatic discharge protection for high-speed integrated circuits, i.e., integrated circuits handling signals having frequencies higher than electrostatic discharge transients.
2. Background of the Related Art
Advances in integrated circuit development continue to increase the density of circuit components that can be fabricated in an integrated circuit (IC) chip. In conjunction with this advance in miniaturization, critical dimensions of the IC such as minimum conductor-to-conductor spacing and layer thicknesses also have been reduced. In particular, insulating layers within the IC structure have become thinner, making ICs more susceptible to electrostatic discharge (ESD) pulses. The pulses are passed to the IC circuit from an input or output pin, and if not properly diverted could deliver a brief but highly destructive charge to the IC circuitry.
As is known in the art, ESD protection circuits can be fabricated in the ICs. Typically, these circuits are disposed on the input and output pads of the ICs and pass normal input signals therethrough while diverting ESD pulses as shown in FIG. 1. Here, an input or output bonding pad 10 of an IC is connected to an internal circuit 20 to be protected from ESD pulses via a conductor 30 (as used herein, xe2x80x9cinput/output bonding padxe2x80x9d denotes that the bonding pad may be used for receiving input signals, providing output signals, or both). Desired signals pass in one or both directions between the bonding pad 10 and the internal circuit 20. Were the IC to have no ESD protection, an ESD pulse appearing at the bonding pad 10 would be conducted via conductor 30 to the internal circuit 20, possibly damaging or destroying it by, e.g., shorting through one or more oxide layers in the IC. However, ESD protection circuit 40 is activated by the relatively high voltage levels (relative to the IC""s internal supply voltage) of the ESD pulses and establishes a low-resistance conductive path between conductor 30 and the ground connection to shunt the ESD pulse away from the internal circuit 20.
As one of ordinary skill in the art will recognize, in practice most protected circuits are equipped with not only one ESD protection circuit 40 between conductor 30 and system ground or Vss, but also with another between conductor 30 and a positive source of potential, such as VDD.
This allows the ESD pulse to be discharged either through the Vss or VDD pad. However, FIG. 1 shows only a single ESD device 40 in the interests of simplicity and ease of explanation.
A typical ESD device 40 as described above is shown in FIG. 2. Here, an N-channel MOS transistor 50 is connected between conductor 30 and Vss. A resistor 70 is connected between the gate of transistor 50 and Vss. A capacitor 60 (which may be a parasitic capacitance of transistor 50 or a separate component) is connected between conductor 30 and the gate of transistor 50. Transistor 50 has a parasitic bipolar mode of operation designated by transistor 50xe2x80x2. The transistor 50 is very wide with a short channel length, e.g., 300 xcexcm wide by 0.5 xcexcm long, to be capable of efficiently shunting the current due to an ESD event (the current due to an ESD event is proportional to the amount of static charge deposited on the IC, and the current is typically between a few tenths of an ampere and a few amperes). By effectively choosing the values of capacitor 60 and resistor 70, the gate of transistor 50 will rise to a voltage of about 1 volt when an ESD event occurs and the voltage on node A rises above a trigger voltage of about 4.0 to 7.5 volts, depending on the IC fabrication technology in use. When the transistor 50 is turned on by such an ESD event, bipolar conduction through transistor 50xe2x80x2 will begin and continue until the voltage on node A falls below the trigger voltage level.
While this arrangement is workable in some applications, the ESD device 40 typically presents a relatively large capacitive loading 40xe2x80x2 (on the order of a few picofarads) to the bonding pad 10 and internal circuit 20. This limits the maximum frequency of desired signals which can be exchanged between bonding pad 10 and internal circuit 20.
Prior art attempts at ameliorating this effect have reduced the size of the ESD protection transistor to lessen the capacitive loading to the IC; however, this necessarily reduces the level of protection afforded by the ESD protection circuit. As the frequency of signals processed by the IC increases, the ESD protection transistor becomes too small to be effective.
It is an object of the present invention to overcome the above shortcomings of the prior art.
It is another object of the present invention to provide a circuit for ESD protection which minimizes the capacitive loading on the inputs and outputs of the circuit which it protects.
It is a further object of the present invention to provide a circuit for ESD protection which is particularly useful with circuits processing high frequency signals.
It is still another object of the present invention to provide a circuit for ESD protection which provides effective ESD protection in high-frequency environments.
It is yet another object of the present invention to provide a circuit for ESD protection which provides effective ESD protection for circuits processing signals at frequencies above those of ESD pulses.
The above objects are achieved according to a first aspect of the present invention by providing an ESD protection circuit which uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while isolating its capacitive load on the main circuit when presented with desired signals which are higher in frequency than ESD pulses. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires.